Verilog

Verilog is a hardware description language (HDL): a domain-specific notation for describing and verifying digital circuits. It is the working language of FPGA and ASIC design — you write logic, not programs.

Purpose

Verilog describes electronic hardware at the register-transfer level (RTL): which registers exist, how data moves between them on clock edges, and how outputs combine through combinational logic.

The Problem It Solves

Before HDLs, digital design meant schematics that were impossible to simulate or reuse. Verilog lets an engineer specify a circuit as text, simulate it before building anything, and let a synthesis tool map it to real gates. Its two styles — continuous assignments for combinational logic and always blocks for clocked behavior — map directly onto hardware concepts.

Where It Fits

Verilog is a quintessential execution-model DSL: the “program” is a description of parallel hardware, not a sequence of instructions. It belongs to this phase as the hardware sibling of software-level low-level languages.

History

Verilog began as a proprietary simulation language and became the industry’s open standard for digital design.

Origins

Phil Moorby and Prabhu Goel designed Verilog at Gateway Design Automation in 1983–84 as a simulation and modeling language. Cadence acquired Gateway in 1990 and opened the language to standardization, which let it spread across the whole industry.

Milestones

1995 — IEEE Std 1364-1995, the first Verilog standard.
2001/2005 — IEEE 1364-2001 (synthesizable RTL improvements) and 1364-2005 (last classic Verilog revision).
2009–2017 — SystemVerilog (IEEE 1800) merges Verilog with verification and modeling features; it is now the mainstream flavor.
Today — open-source tooling (Icarus Verilog, Verilator, GTKWave) makes the whole flow free.

Current Status

Mature and indispensable. Every FPGA vendor flow (Vivado, Quartus), every ASIC project, and most chip-education tracks use Verilog or SystemVerilog; the open-source ecosystem keeps growing.

Stage

Verilog is an industry bedrock: standardized, taught everywhere, and continuously extended.

Maturity

Fully mature. Classic Verilog (IEEE 1364) is frozen; SystemVerilog (IEEE 1800) carries the evolution, including verification constructs such as assertions and constrained-random testing.

Governance & Maintenance

Governed by the IEEE standards process with heavy industry participation (EDA vendors, FPGA makers, chip companies). Tooling ranges from free (Icarus Verilog, Verilator) to commercial (Vivado, Quartus, VCS).

Popularity & Usability

Alongside VHDL, Verilog is one of the two dominant hardware languages — and the more common one for new designs.

Adoption

Industry-wide in FPGA and ASIC design, taught in every digital-design course, and the default language of RISC-V and open-hardware projects.

Learning Curve

Moderate — but the key shift is mental: everything runs in parallel, time is discrete (clock edges), and “variables” are wires or registers. Beginners who write it like software produce hardware that does not work; courses such as HDLBits exist precisely to train that mindset.

Tooling

Free flows are excellent: Icarus Verilog (simulation), Verilator (fast compiled simulation), GTKWave (waveforms), and EDA Playground (browser, no install).

Use Cases

Any digital circuit that will become silicon or an FPGA configuration is described in an HDL.

Primary Domains

FPGA development: signal processing, embedded control, network acceleration, hardware accelerators.
ASIC and SoC design: processors, memory controllers, peripherals, and the verification that proves them correct.
Open-source CPUs: essentially every RISC-V core (e.g. PicoRV32, VexRiscv) is written in Verilog or SystemVerilog.

Strengths

Parallel semantics that match hardware, a synthesizable subset that maps directly to gates, decades of libraries, and simulation that catches bugs before fabrication.

Weak Spots

Event-driven simulation is slow at scale, and classic Verilog lacks modern verification ergonomics (hence SystemVerilog plus UVM). The language also stays far from software abstractions: no strings, no objects, no OS.

Performance

Hardware “performance” has two very different sides: simulation speed and silicon speed.

Execution Model

Simulators evaluate the design’s event queue: signals change, blocks wake, delays tick. That model is faithful but slow. Verilator instead compiles Verilog to C++/SystemC and is widely cited as 2–10x faster (and up to 100x in favorable cases) than interpreted event-driven simulation.

Published Claims

Synthesis tool vendors publish density and frequency numbers for their mapping, but the honest statement is: the language does not set the clock speed — the quality of the RTL and the synthesis flow do. What Verilog decides is how quickly you can simulate and iterate on that RTL.

Example

A minimal, synthesizable 4-bit counter plus the testbench that simulates it — the classic first Verilog pair.

The Counter Module

// counter.v — a 4-bit counter (RTL), synthesizable
module counter (
    input  wire       clk,   // clock: rising edge advances the count
    input  wire       rst,   // synchronous reset
    output reg  [3:0] count  // the 4-bit count value
);
    always @(posedge clk) begin
        if (rst)
            count <= 4'd0;      // reset wins over increment
        else
            count <= count + 4'd1;
    end
endmodule

The Testbench & How to Run

// tb_counter.v — no synthesis; only the simulator sees this
`timescale 1ns/1ps
module tb_counter;
    reg  clk = 0;
    reg  rst = 1;
    wire [3:0] count;

    counter uut (.clk(clk), .rst(rst), .count(count));

    always #5 clk = ~clk;          // 10 ns clock period
    initial begin
        #10 rst = 0;               // release reset after two edges
        #40 $display("count = %0d", count);
        #10 $finish;
    end
endmodule

Build and run with the free Icarus Verilog toolchain:

iverilog -o counter.out counter.v tb_counter.v   # compile both files
vvp counter.out                                  # simulate
gtkwave counter.vcd                              # inspect the waveform

The always block is the heart of the dialect: it says “on every rising clock edge, do this” — parallel hardware, not a loop.

Learn More

Official sources and free materials; the full categorized catalog is on the References & Downloads page.